Modulo sum of two variables in binary system is like this,

The gate performs this modulo sum operation without including carry is known as **XOR gate**. An XOR gate is normally two inputs logic gate where, output is only logical 1 when only one input is logical 1. When both inputs are equal, that is either both are 1 or both are 0, the output will be logical 0. This is the reason an **XOR gate** also called anti-coincidence gate or inequality detector. This gate is called as XOR or exclusive OR gate because, its output is only 1 when one of its input is exclusively 1.

The truth table of XOR gate is given below,

The binary operation of above truth table is known as exclusive OR operation and it is represented as, A ⊕ B. The symbol of exclusive OR operation is represented by a plus ring surrounded by a circle ⊕.

## Realization of Two Inputs XOR Gate

The above expression, A ⊕ B can be simplified as,

Let us prove the above expression.

In first case consider, A = 0 and B = 0.

In second case consider, A = 0 and B = 1.

In third case consider, A = 1 and B = 0.

In fourth case consider, A = 1 and B = 1.

So it is proved that, the Boolean expression for A ⊕ B is AB ̅ + ĀB, as this Boolean expression satisfied all output states respect to inputs conditions, of an **XOR gate**.

From this Boolean expression one can easily realize the logical circuit of an XOR gate and this will be as show,

## Logical Symbol of XOR Gate

An XOR gate is logically represented as,

## More than Two Inputs XOR Gate

As we told already, that XOR gates are two inputs gate, but XOR operation of more than two inputs then can be realized by using more than one or two inputs **XOR gate**. More than two inputs XOR operation is that, when odd number of inputs in the gate are 1, the output is 1 and when none or even number of inputs are 1, the output is logical 0.

## Realization of more than Two inputs XOR Gate

Let us realize an XOR gate with three inputs A, B, and C.

Now, as per definition of XOR operation with more than three inputs, the truth table would be,

This truth table can be elaborated as,

From the above elaborated truth table it is found that, XOR operation of three binary variables is equivalent to, XOR operation one variable with result of XOR operations of other two variables.

From above truth table,

## XNOR Gate

**XNOR gate** is a NOT gate followed by an XOR gate. As we know that XOR operation of inputs A and B is A ⊕ B, therefore XNOR operation those inputs will be (A + B) ̅. That means, output of XOR gate is inverted in XNOR gate. In XOR operation, the output is only 1 when only one input is 1. The output is logical 0 when both inputs are same that means they are either 1 or 0. But in the case of XNOR gate, the output is 0 when only one input is 0 and the output is 1 when both inputs are same that is either both of them are 0 or 1.

The truth table of the **XNOR gate** is shown below,

The logical XNOR operation is represented by ⊙. That is a dot surrounded by circle. The expression of XNOR operation between variable A and B is represented as A ⊙ B.

Now again, the truth table is satisfied by the equation AB + ĀB ̅.

Hence, it is proved that A ⊙ B = AB + ĀB ̅. The same can be proved by using K-map also.

## Realization of XNOR Gate

The expression of XNOR operation can be realized by using two NOT gates, two AND gates and one OR gate as followers,

The symbol of XNOR gate.

## Three Inputs of XNOR Gates

Like **XOR gate**, XNOR gate only exists with two inputs but for XNOR operation with more than two inputs, we have to use more than one XNOR gates. XNOR operation with more than two inputs is like that, when there are odd numbers of inputs are in high or logical 1 condition, the output will be 0 in otherwise the output will be 1.

Now,

From this elaborate truth table, the logical symbol of three inputs XNOR gate can be represented as,

### Application of XOR Gate

The main application of the Exclusive OR gate is in the operation of half and full adder. If we look at the truth table carefully we will find that the first three results are totally satisfying the process of binary addition but in the last input sequence i.e. when both the inputs are 1 the result according to the rule of addition should be 0 with a carry 1. In the truth table we are getting the desired 0 but a missing 1.

To solve this problem during designing the circuit of an adder an AND gate is added to the **Ex-OR gate** in parallel. We will show the circuit of the adder in detail.

From the above diagram, we can see that in the circuit of a half adder the two inputs are going through an Exclusive-OR gate and through an AND gate parallelly. And with this circuit’s operation we get the total process of binary addition smoothly.

Pseudo-random number generation.

To model a linear feedback shift register Ex-OR gates are used and they generate random sequence of bits.