The binary digits are 0 and 1. Hence, there must be four possible combinations of binary addition of two binary bits In the above list, first three binary operations result in one bit but fourth one result in two bits. In one bit binary addition, if augend and addend are 1, the sum will have two digits. The higher significant bit (HSB) or Left side bit is called carry and the list significant bit (LSB) or right side bit of the result is called sum bit. The logical circuit performs this one bit binary addition is called half adder.

In first three binary additions, there is no carry hence the carry in these cases are considered as 0.

- We have to add first list significant bit (LSB) of both 4bits binary number first and this will result a two bits binary number. Here, LSB of 1101 and 0111 are 1, hence 1 + 1 = 10. The LSB of 10 is 0 and higher significant bit (HSB) is 1.
- The LSB of the result is sum and to be put at the list significant position of the final result of the sum, and HSB of the two bits results will be carry and to be added with next higher significant bit of two 4bits augend and addend are 0 and 1 and the carry of previous result i.e. 1 to be added with 0 and 1.
- After this addition, that is next higher than list significant bit of bits of both binary augend and addend and it is previous carry we get another two bits result. This also has carry and sum. Here also we will write sum at final result and add the carry to the next higher significant bits of augend and addend. This will continue up to most significant bit of augend and addend.

Let us add 1011 with 1101. As there is no previous carry C

4 bit parallel adder IC is 4008. In n bit parallel adder, output carry terminal of one IC would be connected with input carry terminal of next IC.

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