# Parallel Adder

on 24/2/2012 & Updated on 28/8/2018Adders are the combinatorial circuits which are used to add two binary numbers. The nature of the adders chosen depends on the characteristics of the binary numbers which need to be added. Say for example, if one needs to add two single bit binary digits, then one can use half adder while if there is an additional carry which needs to be added along with them, then one may resort to the use of full adder. However what if we want to add a binary number which has multiple bits in it. In such a case, the need arises to use a

Rate the page.**.***parallel adder*## Structure of Parallel Adder

Parallel adder is nothing but a cascade of several full adders. The number of full adders used will depend on the number of bits in the binary digits which require to be added. Such a n-bit adder formed by cascading n full adders (FA_{1}to FA_{n}) is as shown by Figure 1 and is used to add two n-bit binary numbers .__Related pages__

Here, every single bit of the numbers to be added is provided at the input pins of every single full adder. That is, the first bits A_{1} and B_{1} are provided as the inputs to full adder (FA_{1}), the second bits A_{2} and B_{2} to the inputs of full adder 2 (FA_{2})… and the last bits A_{n} and B_{n} to the n^{th} full adder FA_{n}. Next, the carry out pin of each full adder in the circuit is connected to the carry in pin of its succeeding full adder (except in the case of last full adder). For example, the carry out pin of FA_{1} (Co_{1}) is connected to carry in pin of FA_{2} (Ci_{2}), the carry out pin of FA_{2} (Co_{2}) is connected to carry in pin of FA_{3} (Ci_{3}) and so on and so forth.

## Working of Parallel Adder

In the circuit shown by Figure 1, first, FA_{1}adds A_{1}with B_{1}to generate S_{1}(the first bit of sum output) and Co_{1}. Next, FA_{2}uses this Co_{1}as its carry in bit and adds it with its input bits A_{2}and B_{2}to generate the second bit of the sum output S_{2}and Co_{2}. Next, this Co_{2}is considered as an input by FA_{3}which adds it with the bits A_{3}and B_{3}. This process continues till the nth full adder in the sequence which adds the carry out bit of (n-1)^{th}full adder (Co_{n-1}) with its inputs A_{n}and B_{n}. When this happens, we would get the output bits S_{n}and Co_{n}which are the last bits of our sum output and the expected carry bit, respectively.## Drawback of Parallel Adders

From the discussion presented we can say that in the case of n-bit**parallel adder**, each adder has to wait for the carry term to be generated from its preceding adder in order to finish its task of adding. This can be visualized as if the carry term propagates along the chain in the fashion of a ripple. Thus these kind of adders are even referred to as ripple carry adders. Further, the delay associated with the travelling of carry bit is called carry propagation delay and is found to worsen with an increase in the length of the binary numbers which require to be added. For example, if each full adder is considered to have a delay of 10 ns, then the total delay required to produce the output of a 4-bit**parallel adder**would be 4 × 10 = 40 ns.Rating = 4.12 & Total votes = 8