# NMOS Logic and PMOS Logic

**PMOS**, the

**NMOS**and the integrated injection logic (I2L). The first two are briefly discussed in this section.

## PMOS Logic

The**PMOS logic**family uses P-channel MOSFETS. Figure (a) shows an inverter circuit using PMOS logic. MOSFET Q

_{1}acts as an active load for the MOSFET switch Q

_{2}. For the circuit shown,

GND and −V_{DD} respectively represent a logic ‘1’ and a logic ‘0’ for a positive logic system. When the input is grounded (i.e. logic ‘1’), Q_{2} remains in cut-off and −V_{DD} appears at the output through the conducting Q_{1}. When the input is at −V_{DD} or near −V_{DD}, Q_{2} conducts and the output goes to near-zero potential (i.e. logic ‘1’). Figure (b) shows a PMOS logic based two-input NOR gate. In the logic arrangement of Fig.(b), the output goes to logic ‘1’ state (i.e. ground potential) only when both Q_{1} and Q_{2} are conducting. This is possible only when both the inputs are in logic ‘0’ state. For all other possible input combinations, the output is in logic ‘0’ state, because, with either Q_{1} or Q_{2} nonconducting, the output is nearly −V_{DD} through the conducting Q_{3}.

The circuit of Fig.(b) thus behaves like a two-input NOR gate in positive logic. It may be mentioned here that the MOSFET being used as load [Q_{1} in Fig. (a) and Q_{3} in Fig. (b)] is designed so as to have an ON-resistance that is much greater than the total ON-resistance of the MOSFETs being used as switches

[Q_{2} in Fig. (a) And

Q_{1} and Q_{2} in Fig.(b)].

## NMOS Logic

The NMOS logic family uses N-channel MOSFETS. N-channel MOS devices require a smaller chip area per transistor compared with P-channel devices, with the result that NMOS logic offers a higher density. Also, owing to the greater mobility of the charge carriers in N-channel devices, the NMOS logic family offers higher speed too. It is for this reason that most of the MOS memory devices and microprocessors employ NMOS logic or some variation of it such as VMOS, DMOS and HMOS. VMOS, DMOS and HMOS are only structural variations of NMOS, aimed at further reducing the propagation delay. Figures (a), (b) and (c) respectively show an inverter, a two-input NOR and a two-input NAND using**NMOS logic**. The logic circuits are self-explanatory.

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