Parallel Subtractor

The combinatorial circuits which are used to subtract two binary numbers are called Subtractors. When the binary numbers to be subtracted are of single bits, then, we can use a half subtractor to accomplish the task while if we need to subtract three binary numbers of single bits (among which two will generally be inputs while the other will be the borrow), we will have to use full subtractor. Now what if we desire to subtract two n-bit binary numbers? This is the case which demands for the use of n–bit parallel subtractor.

Structure of Parallel Subtractor

Generally when one needs to subtract the binary number 2 from binary number 1, then the binary number 2 will be expressed in its 2’s complement form and then added with the binary number 1 (nothing but 2’s complement form of binary subtraction).

Next, 2’s complement of a number can be obtained by taking 1’s complement of the number and then by adding 1 to its least significant bit (LSB). Further, taking 1’s complement means nothing but negating the binary number. From the discussion presented, one can conclude that inorder to accomplish subtraction, one can use the same circuit as that for addition (more on this in the article “Parallel Adder”) provided we have the number ‘to be subtracted’ in its 2’s complement form. This task of expressing the number in 2’s complement form may be brought about by first using NOT gates to invert the bits in the binary number. However, to add 1 at LSB, one can make use of the first adder in the sequence of n full adders used in the circuit just by providing logic high at its carry in (Ci1) pin. As a result, one can design the n-bit parallel subtractor as shown in Figure 1. parallel subtractor Here the binary number is the minuend and the binary number is the subtrahend. Further, the sum outputs of each and every adder actually correspond to the difference bits (the expected result) while the carry out pin of the last full adder (Con) will be nothing but the resultant borrow.

Apart from this kind of circuit, one can even design the parallel subtractor using just a cascaded array of full subtractors. Figure 2 shows such an-bit parallel subtractor designed using n full subtractors (FS1 to FSn) joined in a way similar to that of in the case of n-bit parallel adder. parallel subtractor The working of such a circuit is straight forward and is very similar to that of a parallel adder. As a result, even parallel subtractors are prone to the effect of ripple propagation which results in the delayed output. That is, if the dealy associated with each of the full subtractor is T seconds, then the overall difference bits (D1D2…Dn) and borrow bit (Br) are obtained only after n Tseconds.


Closely Related Articles Digital ElectronicsBoolean Algebra Theorems and Laws of Boolean AlgebraDe Morgan Theorem and Demorgans LawsTruth Tables for Digital LogicBinary Arithmetic Binary AdditionBinary SubtractionSimplifying Boolean Expression using K MapBinary DivisionExcess 3 Code Addition and SubtractionK Map or Karnaugh MapSwitching Algebra or Boolean AlgebraBinary MultiplicationMore Related Articles Binary Adder Half and Full AdderBinary SubstractorSeven Segment DisplayBinary to Gray Code Converter and Grey to Binary Code ConverterBinary to BCD Code ConverterAnalog to Digital ConverterDigital Encoder or Binary EncoderBinary DecoderBasic Digital CounterDigital ComparatorBCD to Seven Segment DecoderParallel AdderParallel Adder or SubtractorMultiplexerDemultiplexer555 Timer and 555 Timer WorkingLook Ahead Carry AdderOR Operation | Logical OR OperationAND Operation | Logical AND OperationLogical OR GateLogical AND GateNOT GateUniversal Gate | NAND and NOR Gate as Universal GateNAND GateDiode and Transistor NAND Gate or DTL NAND Gate and NAND Gate ICsX OR Gate and X NOR GateTransistor Transistor Logic or TTLNOR GateFan out of Logic GatesINHIBIT GateNMOS Logic and PMOS LogicSchmitt GatesLogic Families Significance and Types of Logic FamiliesBinary Number System | Binary to Decimal and Decimal to Binary ConversionBinary to Decimal and Decimal to Binary ConversionBCD or Binary Coded Decimal | BCD Conversion Addition SubtractionBinary to Octal and Octal to Binary ConversionOctal to Decimal and Decimal to Octal ConversionBinary to Hexadecimal and Hex to Binary ConversionHexadecimal to Decimal and Decimal to Hexadecimal ConversionGray Code | Binary to Gray Code and that to Binary ConversionOctal Number SystemDigital Logic Gates2′s Complement1′s ComplementASCII CodeHamming Code2s Complement ArithmeticError Detection and Correction Codes9s complement and 10s complement | SubtractionSome Common Applications of Logic GatesKeyboard EncoderAlphanumeric codes | ASCII code | EBCDIC code | UNICODELatches and Flip FlopsS R Flip Flop S R LatchActive Low S R Latch and Flip FlopGated S R Latches or Clocked S R Flip FlopsD Flip Flop or D LatchJ K Flip FlopMaster Slave Flip FlopRead Only Memory | ROMProgrammable Logic DevicesProgrammable Array LogicApplication of Flip FlopsShift RegistersBuffer Register and Controlled Buffer RegisterData Transfer in Shift RegistersSerial In Serial Out (SISO) Shift RegisterSerial in Parallel Out (SIPO) Shift RegisterParallel in Serial Out (PISO) Shift RegisterParallel in Parallel Out (PIPO) Shift RegisterUniversal Shift RegistersBidirectional Shift RegisterDynamic Shift RegisterApplications of Shift RegistersUninterruptible Power Supply | UPSConversion of Flip FlopsJohnson CounterSequence GeneratorRing CounterNew Articles Acidity Test of Transformer Insulating OilMagnetic FluxRing CounterDischarging a CapacitorCharging a Capacitor