# Parallel in Serial Out (PISO) Shift Register

**Parallel In Serial Out (PISO) shift registers**, the data is loaded onto the register in parallel format while it is retrieved from it serially. Figure 1 shows a

**PISO shift register**which has a control-line (SH/) and combinational circuit (AND and OR gates) in addition to the basic register components (flip-flops) fed with clock and clear pins. Here SH/ control line is used to select the functionality of the shift register amongst shift or load at a given instant of time. This is because when the SH/ line is made low, A

_{2}AND gates of all the combinational circuits become active while A

_{1}gates become inactive.

Thus the bits of the input data word (Data in) appearing as inputs to the gates A_{2} are passed on as the outputs of OR gates at each individual combinational circuit. This causes the individual bits of the Data in to be loaded/stored into respective flip-flops at the appearance of first leading edge of the clock (except the bit B_{1} which gets directly stored into FF_{1} at the first clock tick). This indicates that all the bits of the input data word are stored into the register components at the same clock tick.
Next, SH/ line is driven high to activate the gates A_{1} of the combinational circuits which inturn disables the gates A_{2}. This causes output bit of each flip-flop to appear at the output of the OR gate driving the very-next flip-flop (except the last flip-flop FF_{n}) i.e. output bit of FF_{1} (Q_{1}) appears as the output of OR gate 1 (O_{1}) connected to D_{2}; Q_{2} = output of O_{2} = D_{3} and so on. At this stage, if the rising edge of the clock pulse appears, then Q_{1} appears at Q_{2}, Q_{2} appears at Q_{3}, … and Q_{n-1} appears at Q_{n}. This is nothing but right-shift of the data stored within the register by one-bit. Similarly it is seen that for each of the further clock pulses applied, one bit exits the PISO shift register through the output pin of n^{th} flip-flop (Data out = Q_{n} of FF_{n}), which is nothing but the serial output. Thus one requires n clock cycles to obtain the entire n-bit input data word as a serial output of PISO shift register.
The truth table of the **PISO shift register** emphasizing the loading and retrieval processes is shown by Table I, while the corresponding wave forms are shown by Figure 2.
By slightly modifying the design of Figure 1, one can make the data bits within the register to shift from right to left, thus obtaining a left-shift PISO shift-register (Figure 3). However the basic working principle remains unaltered.

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