Parallel in Serial Out (PISO) Shift Register

In Parallel In Serial Out (PISO) shift registers, the data is loaded onto the register in parallel format while it is retrieved from it serially. Figure 1 shows a PISO shift register which has a control-line and combinational circuit (AND and OR gates) in addition to the basic register components (flip-flops) fed with clock and clear pins.

Here control line is used to select the functionality of the shift register amongst shift or load at a given instant of time. This is because when the line is made low, A₂ AND gates of all the combinational circuits become active while A₁ gates become inactive.

Related pages

Shift Registers

Applications of Shift Registers

Universal Shift Registers

Bidirectional Shift Register

Dynamic Shift Register

Buffer Register and Controlled Buffer Register

Data Transfer in Shift Registers

Serial in Serial Out (SISO) Shift Register

Serial in Parallel Out (SIPO) Shift Register

Parallel in Serial Out (PISO) Shift Register

Parallel in Parallel Out (PIPO) Shift Register

Thus the bits of the input data word (Data in) appearing as inputs to the gates A₂ are passed on as the outputs of OR gates at each individual combinational circuit. This causes the individual bits of the Data in to be loaded/stored into respective flip-flops at the appearance of first leading edge of the clock (except the bit B₁ which gets directly stored into FF₁ at the first clock tick). This indicates that all the bits of the input data word are stored into the register components at the same clock tick.

Next, line is driven high to activate the gates A₁ of the combinational circuits which inturn disables the gates A₂. This causes output bit of each flip-flop to appear at the output of the OR gate driving the very-next flip-flop (except the last flip-flop FF_n) i.e. output bit of FF₁ (Q₁) appears as the output of OR gate 1 (O₁) connected to D₂; Q₂ = output of O₂ = D₃ and so on. At this stage, if the rising edge of the clock pulse appears, then Q₁ appears at Q₂, Q₂ appears at Q₃, … and Q_n-1 appears at Q_n.

This is nothing but right-shift of the data stored within the register by one-bit. Similarly it is seen that for each of the further clock pulses applied, one bit exits the PISO shift register through the output pin of n^th flip-flop (Data out = Q_n of FF_n), which is nothing but the serial output. Thus one requires n clock cycles to obtain the entire n-bit input data word as a serial output of PISO shift register. The truth table of the PISO shift register emphasizing the loading and retrieval processes is shown by Table I, while the corresponding wave forms are shown by Figure 2. By slightly modifying the design of Figure 1, one can make the data bits within the register to shift from right to left, thus obtaining a left-shift PISO shift-register (Figure 3). However the basic working principle remains unaltered.