# INHIBIT Gate

Published on 24/2/2012 and last updated on Monday 2nd of July 2018 at 07:11:30 PMWe have already discussed a lot about the logical gates of digital electronics system. We know about the three basic gates i.e. AND gate, OR gate and NOT gates and the other gates like NAND, NOR, EX-OR, EX-NOR etc. Now when we know about the basics of logic circuit we will discuss about a special type of gate i.e.

Here the term INHIBIT means the gate which has it produces a certain or fixed output whatever be the inputs or even the inputs are changed. We can explain this with an illustration, suppose there is a four input NOR gate which a one has fixed input logic level‘1’. Then we will get the fixed output ‘0’ irrespective of whatever may be the other inputs. As one input is permanently ‘1’ the output will be always ‘0’. So we can say that fixing this one input permanently inhibits the function of the gate. This gate will work like a normal NOR gate only when that input is changed to ‘0’ level. The above illustration explains the INHIBIT function.

**INHIBIT gate**. Many times there arise many situations when the logical signals are needed to be either enabled or inhibited which depends upon certain other control inputs. This is where the need of this type of logic gate arises.Here the term INHIBIT means the gate which has it produces a certain or fixed output whatever be the inputs or even the inputs are changed. We can explain this with an illustration, suppose there is a four input NOR gate which a one has fixed input logic level‘1’. Then we will get the fixed output ‘0’ irrespective of whatever may be the other inputs. As one input is permanently ‘1’ the output will be always ‘0’. So we can say that fixing this one input permanently inhibits the function of the gate. This gate will work like a normal NOR gate only when that input is changed to ‘0’ level. The above illustration explains the INHIBIT function.

This function is also available in integrated circuit form for an AND gate. It is basically an AND gate which has one of its inputs negated by an inverter. The input which is negated acts to inhibit the gate. Or we can say the gate will behave like an AND gate only when the negated input is set at a logic level ‘0’. Now we will see this through the circuit symbol and truth table for a four input **INHIBIT gate**.

Now in the above diagram if all the inputs of the gate is permanently tied to logic level ‘1’ then the logic ‘0’ at the INHIBIT input will produce a logic ‘1’ at the output and a logic ‘1’ at the inhibit input will result in a logic ‘0’ output. Now we will look at the truth table of the above drawn gate.

A | B | C | D | Y |

0 | 0 | 0 | 0 | 0 |

0 | 0 | 0 | 1 | 0 |

0 | 0 | 1 | 0 | 0 |

0 | 0 | 1 | 1 | 0 |

0 | 1 | 0 | 0 | 0 |

0 | 1 | 0 | 1 | 0 |

0 | 1 | 1 | 0 | 0 |

0 | 1 | 1 | 1 | 0 |

1 | 0 | 0 | 0 | 0 |

1 | 0 | 0 | 1 | 0 |

1 | 0 | 1 | 0 | 0 |

1 | 0 | 1 | 1 | 0 |

1 | 1 | 0 | 0 | 0 |

1 | 1 | 0 | 1 | 0 |

1 | 1 | 1 | 0 | 1 |

1 | 1 | 1 | 1 | 0 |

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