Gated S R Latches or Clocked S R Flip Flops
In latch we so far discussed can change its state instantaneously on the application of required inputs conditions. They are asynchronous latches. On the other hand, a gated S-R latch can only change its output state when there is an enabling signal along with required inputs. That means the inputs can only act upon when the latch is enabled otherwise there will be no change in output state even required inputs are applied. In other words, the latch is active when ENABLE signal is HIGH and it is inactive when ENABLE signal is LOW. This HIGH LOW enable signal is applied to the gated latch in the form of clocked pulses.
So, gated S-R latch is also called clocked S-R Flip flop or synchronous S-R latch.Since this latch responds to the applied inputs only when the level of the clock pulse is high, this type of flip-flop is also called level triggered flip-flop. The logical circuit of a Gated S-R Latch or Clocked S-R Flip-Flop is shown below.
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