Gated SR Latch or Clocked SR Flip Flops: Truth Table & Explanation

What is a Gated SR Latch?

A gated SR latch (or clocked SR Latch) can only change its output state when there is an enabling signal along with required inputs. For this reason it is also known as a synchronous SR latch. Conversely, latches that can change its state instantaneously on the application of its required inputs conditions are known as asynchronous latches.

That means the inputs can only act upon when the latch is enabled otherwise there will be no change in output state even required inputs are applied. In other words, the latch is active when ENABLE signal is HIGH and it is inactive when ENABLE signal is LOW. This HIGH LOW enable signal is applied to the gated latch in the form of clocked pulses.

So, gated S-R latch is also called clocked S-R Flip flop or synchronous S-R latch.Since this latch responds to the applied inputs only when the level of the clock pulse is high, this type of flip-flop is also called level triggered flip flop. The logical circuit of a Gated SR Latch or Clocked SR Flip-Flop is shown below.
Gated S R Latches

Clocked S R Flip Flops

Gated SR Latch Truth Table

The truth table for a gated SR latch or gated SR flip flop has been shown in the table below.

There are also D Latches, JK Flip Flops, Active Low SR Flip Flops, and Gated SR Flip Flops. You can learn more about clocked SR flip flops and other logic gates by checking out our full list of logic gates questions.

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