# Active Low S R Latch and Flip Flop

There is one type of latch which is SET when S = 0(LOW), and this latch is known as

**Active Low S R Latch**.This latch is normally designed by using NAND gates. The logical circuit is shown below. In the above logic circuit if S = 0 and R = 1, Q becomes 1. Let us explain how.- NAND gate always gives output 1 when at least one of the inputs is 0.
- So, when S is applied as 0 the output of gate G1 i.e. Q is 1 irrespective of the condition of second input to the gate.
- Now, Q is input of gate G2 so both the inputs of G2 become 1 as R is already 1. So output of G2 is now or 0.
- So whatever may be the previous condition of Q, it always becomes Q = 1 and = 0 when S = 0 and R = 1. This is called SET condition of the latch.

- As we already said, a NAND gate always gives output 1 when at least one of the inputs is 0.
- So when R is applied as 0, the output of gate G2 i.e. is 1 irrespective of the condition of second input Q to the gate.
- So whatever may be the previous condition of , it always becomes 1 this 1 is then fed back to input of gate G1. As here S is already 1, both inputs of G1 are 1. Hence output of G1 i.e. Q will be 0. So Q = 0 and = 1 when, S = 1 and R = 0. This is called RESET condition of the latch.

- First suppose Q is previously 1.
- Now both inputs of G2 are 1 as R = 1 and Q = 1. So output of G2 i.e. is or 0.
- Now the inputs of G1 are 1 and 0 as R = 1 and = 0. So output of G1 i.e. Q is or 1.
- Now suppose Q is previously 0.
- Now the inputs of G2 are 1 and 0 as R = 1 and Q = 0. So output of G2 i.e. is or 1.
- Now both inputs of G1 are 1 as S = 1 and = 1. So output of G1 i.e. Q is or 0.
- So it is proved that Q remains same as it is when, S = 1 and also R = 1.

In the above logic circuit if S = 0 and also R = 0, the condition of Q is totally unpredictable. Let us explain how.

- First suppose Q is previously 0.
- Now both inputs of G2 are 0 as R = 0 and Q = 0. So output of G2 i.e. is or 1.
- Now the inputs of G1 are 0 and 1 as S=0 and = 1. So output of G1 i.e. Q is or 1. That means Q is changed.
- Now Q is 1. So inputs of G2 are 0 and 1 as R = 0 and Q = 1. So output of G2 i.e. is or 1. That means is unchanged.
- Now the inputs of G1 are 0 and 1 as S=0 and = 1. So output of G1 i.e. Q is or 1. That means Q is unchanged.

**S R latch**normally avoided.**Comments/Feedbacks**

Closely Related Articles Latches and Flip FlopsS R Flip Flop S R LatchGated S R Latches or Clocked S R Flip FlopsD Flip Flop or D LatchJ K Flip FlopMaster Slave Flip FlopRead Only Memory | ROMProgrammable Logic DevicesProgrammable Array LogicApplication of Flip FlopsShift RegistersBuffer Register and Controlled Buffer RegisterData Transfer in Shift RegistersSerial In Serial Out (SISO) Shift RegisterSerial in Parallel Out (SIPO) Shift RegisterParallel in Serial Out (PISO) Shift RegisterParallel in Parallel Out (PIPO) Shift RegisterUniversal Shift RegistersBidirectional Shift RegisterDynamic Shift RegisterApplications of Shift RegistersUninterruptible Power Supply | UPSConversion of Flip FlopsJohnson CounterSequence GeneratorRing CounterMore Related Articles Digital ElectronicsBoolean Algebra Theorems and Laws of Boolean AlgebraDe Morgan Theorem and Demorgans LawsTruth Tables for Digital LogicBinary Arithmetic Binary AdditionBinary SubtractionSimplifying Boolean Expression using K MapBinary DivisionExcess 3 Code Addition and SubtractionK Map or Karnaugh MapSwitching Algebra or Boolean AlgebraBinary MultiplicationParallel SubtractorBinary Adder Half and Full AdderBinary SubstractorSeven Segment DisplayBinary to Gray Code Converter and Grey to Binary Code ConverterBinary to BCD Code ConverterAnalog to Digital ConverterDigital Encoder or Binary EncoderBinary DecoderBasic Digital CounterDigital ComparatorBCD to Seven Segment DecoderParallel AdderParallel Adder or SubtractorMultiplexerDemultiplexer555 Timer and 555 Timer WorkingLook Ahead Carry AdderOR Operation | Logical OR OperationAND Operation | Logical AND OperationLogical OR GateLogical AND GateNOT GateUniversal Gate | NAND and NOR Gate as Universal GateNAND GateDiode and Transistor NAND Gate or DTL NAND Gate and NAND Gate ICsX OR Gate and X NOR GateTransistor Transistor Logic or TTLNOR GateFan out of Logic GatesINHIBIT GateNMOS Logic and PMOS LogicSchmitt GatesLogic Families Significance and Types of Logic FamiliesBinary Number System | Binary to Decimal and Decimal to Binary ConversionBinary to Decimal and Decimal to Binary ConversionBCD or Binary Coded Decimal | BCD Conversion Addition SubtractionBinary to Octal and Octal to Binary ConversionOctal to Decimal and Decimal to Octal ConversionBinary to Hexadecimal and Hex to Binary ConversionHexadecimal to Decimal and Decimal to Hexadecimal ConversionGray Code | Binary to Gray Code and that to Binary ConversionOctal Number SystemDigital Logic Gates2′s Complement1′s ComplementASCII CodeHamming Code2s Complement ArithmeticError Detection and Correction Codes9s complement and 10s complement | SubtractionSome Common Applications of Logic GatesKeyboard EncoderAlphanumeric codes | ASCII code | EBCDIC code | UNICODENew Articles Acidity Test of Transformer Insulating OilMagnetic FluxRing CounterDischarging a CapacitorCharging a Capacitor