# D Flip Flop or D Latch

This is why this type of single input Flip flop is called **D-Flip Flop** or **D Latch**. Basic logical representation of D-flip flop is shown below.
D latch can be gated and then the logical circuit can be as follows

**Gated D - Latch**: There are many applications where separate S and R inputs not required. In these cases by creating D flip-flop we can omit the conditions where S = R = 0 and S = R = 1. In D flip-flop if D = 1 then S = 1 and R = 0 hence the latch is set on the other hand if D = 0 then S = 0, and R = 1 hence the latch is reset. We can make this latch as gated latch and then it is called gated D-latch. Like gated S-R latch gated D flip-flop also have ENABLE input. The difference from gated S-R latch is that it has only two inputs D and ENABLE. The above said set and reset conditions of the latch is only seen in the latch when the ENABLE or EN input is high. That means when D = 1 and EN = 1 the gated latch D flip-flop is ENABLE and SET when D = 0 and EN = 1 the latch is ENABLE and RESET but when EN = 0 the latch is DISABLE no question of SET REST. That means at EN = 0, any change in input D does not affect the output (No Change Condition). Again SET means output Q = 1 and RESET means Q = 0 so Q = D or output follows input when EN is High and this is the reason for which it is , an LOW D input makes Q Low, i.e. resets the flip-flop and a High D input makes Q High, i.e. sets the flip-flop. In other words, we can say that the output Q follows the D input when EN is High. So, this latch is said to be transparent. The logic diagram, the logic symbol and the truth table of a gated D-latch are shown in Figure bellow.

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