# D Flip Flop or D Latch: What is it? (Truth Table & Timing Diagram)

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## What is a D Flip Flop (D Latch)?

A D Flip Flop (also known as a D Latch or a ‘data’ or ‘delay’ flip-flop) is a type of flip flop that tracks the input, making transitions with match those of the input D. The D stands for ‘data’; this flip-flop stores the value that is on the data line. It can be thought of as a basic memory cell.

In an active high SR Flip Flop is when S (Set) and R (Reset) both are 0, there will be no change in the output of the latch, and when both S and R are 1 the output of the latch is totally unpredictable. In an active low SR Flip Flop when S and R both are 1, there will be no change in the output of the latch, and when both S and R are 0 the output of the latch is totally unpredictable.

So if both inputs of the flip-flop are the same there will either be a No Change or Invalid output condition. If we avoid these conditions of inputs, there will be either SET or RESET conditions.

There are many applications, where only SET and RESET conditions of the latch are required. In these applications, we can use inputs (S and R) which are always the complement of each other.

This can be designed by a single input (S) to the latch and the R input achieved by inverting this S. This single input is called data input and it is labeled with D.

This is why this type of single input Flip flop is known as a D-Flip Flop or D Latch. The basic logical representation (i.e. circuit diagram) of a D-flip flop is shown below.

A D latch can be gated. These types of D latches are known as gated D latches.

## Gated D Latch

There are many applications where separate S and R inputs not required. In these cases by creating D flip-flop we can omit the conditions where S = R = 0 and S = R = 1. In D flip-flop if D = 1 then S = 1 and R = 0 hence the latch is set on the other hand if D = 0 then S = 0, and R = 1 hence the latch is reset. This is known as a Gated D Latch.

We can make this latch as gated latch and then it is called gated D-latch. Like gated SR latch gated D flip-flops also have ENABLE input. The difference from the gated S-R latch is that it has only two inputs D and ENABLE. The above said set and reset conditions of the latch is only seen in the latch when the ENABLE or EN input is high.

That means when D = 1 and EN = 1 the gated latch D flip-flop is ENABLE and SET when D = 0 and EN = 1 the latch is ENABLE and RESET but when EN = 0 the latch is DISABLE no question of SET REST. That means at EN = 0, any change in input D does not affect the output (No Change Condition).

Again SET means output Q = 1 and RESET means Q = 0 so Q = D or output follows input when EN is High and this is the reason for which it is that a LOW D input makes Q Low, i.e. resets the flip-flop and a High D input makes Q High, i.e. sets the flip-flop.

In other words, we can say that the output Q follows the D input when EN is High. So, this latch is said to be transparent.

## D Flip Flop Truth Table

The logic diagram, the logic symbol, and the truth table of a gated D-latch are shown in the figures below.

There are also JK Flip Flops, SR Flip Flops, and a Clocked SR Latch.

You can learn more about D flip flops and other logic gates by checking out our full list of logic gates questions.

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