Programmable Array Logic

Programmable Array Logic (PAL) is a type of Programmable Logic Device (PLD) used to realize a particular logical function. PALs comprise of an AND gate array followed by an OR gate array as shown by Figure 1. However it is to be noted that here only the AND gate array is programmable unlike the OR gate array which has a fixed logic. This is because here the inputs are fed to the AND gates through fuses (shown in blue), which act as programmable links. Programmable-AND and fixed-OR structure of PALs make them less flexible from programming point of view when compared with Programmable Logic Arrays (PLAs). However due to the same reason PALs are less expensive than PLAs.

programmable array logic
Figure 2 shows the internal structure of a PAL with m inputs and n outputs. Each of the input line is showed to pass through the buffers and/or inverters. All of these inputs are connected each and every AND gate present in the PAL.

Further this connection matrix is programmable (red box in Figure 2) which lets the user to decide the connection between the input lines and the AND gates. This means that one has to connect each and every input line to either single or multiple AND gate(s), depending on the logic. This causes one to realize the logical ‘and’ functionality between the input lines. Further the outputs of the AND gate array are fed as inputs to the OR gates via hard-wired connections (shown by blue box in Figure 2), which are fixed and hence unalterable. Moreover it is to be noted that the output of every AND gate is not fed to every OR gate. For example, OR gate 1 (O1) is has multiple inputs including the outputs of AND gate 1 (A1), AND gate 2 (A2) and AND gate p (Ap).

However OR gate n (On) has only two inputs which are the outputs of AND gates A1 and Ap. As these connections are fixed, one has to pay attention while establishing the connection to realize the logical ‘or’ functionality of the product-terms obtained as outputs from AND gate array.
programmable array logic
Finally there are n output lines of the OR gate array resulting in n output PAL realizing the required logic in sum-of-products (SOP) form. The PAL shown in Figure 2 can be addressed as m-input, p-product-term, n-output PAL. However it is to be noted that the number of inputs, AND gates and OR gates present in the PAL are all independent i.e. one PAL can have 3 inputs, 8 AND gates and 4 outputs (and thus 4 OR gates).

All PALs can be electrically programmed using bit files through device programmers. Further device feeders and gang programmers can be used in order to program more than one PAL. Common programming languages in use include PAL assembler (PALASM), Compiler for Universal Programmable Logic (CUPL) and Advanced Boolean Expression Language (ABEL).

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