# Parallel in Parallel Out (PIPO) Shift Register

**Parallel In Parallel Out (PIPO) shift registers**are the type of storage devices in which both data loading as well as data retrieval processes occur in parallel mode. Figure 1 shows a PIPO register capable of storing n-bit input data word (Data in). Here each flip-flop stores an individual bit of the data in appearing as its input (FF

_{1}stores B

_{1}appearing at D

_{1}; FF

_{2}stores B

_{2}appearing at D

_{2}… FF

_{n}stores B

_{n}appearing at D

_{n}) at the instant of first clock pulse. Further, at the same instant, the bit stored in each individual flip-flop also appears at their respective output pins (Q

_{1}= D

_{1}; Q

_{2}= D

_{2}… Q

_{n}= B

_{n}). This indicates that both data storage as well as data recovery occur at a single (and at the same) clock pulse in PIPO registers.

However one has to note that the PIPO register shown in Figure 1 is not capable of shifting the data bits. In order to convert PIPO register of Figure 1 into PIPO shift register, one has to modify its circuit by adding combinational circuit and control line SH/ as shown by Figure 2.
Here if SH/ line goes low, A_{2} AND gates of all the combinational circuits become active while A_{1} gates become inactive.

Thus the bits of the input data word (Data in) appearing as inputs to the gates A_{2} are passed on as the OR gate outputs which are further loaded/stored into respective flip-flops at the appearance of first leading edge of the clock (except the bit B_{1} which gets directly stored into FF_{1} at the first clock tick). This indicates that all the bits of the input data word are stored into the register components at the same clock tick. At the same time, these bits also appear at the output pins of the respective flip-flops thus yielding parallel-output data word at the same clock tick.

Further when SH/ line is made high, A_{1} gates of all the combinational circuits enable while A_{2} gates get disabled. This causes the output bit of each flip-flop to appear at the output of the OR gate driving the very-next flip-flop (except the last flip-flop FF_{n}) i.e. output bit of FF_{1} (Q_{1}) appears as the output of OR gate 1 (O_{1}) connected to D_{2}; Q_{2} = output of O_{2} = D_{3} and so on. At this stage, if the rising edge of the clock pulse appears, then Q_{1} appears at Q_{2}, Q_{2} appears at Q_{3}, … and Q_{n-1} appears at Q_{n}. This is nothing but right-shift of the data stored within the register by one-bit. This working is further emphasized in the Table I and Figure 3.
Similar to the right-shift PIPO shift register, there can also be a left-shift PIPO shift register as shown by Figure 4. Nevertheless the mode of working remains the same.

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