Data Transfer in Shift Registers

Shift registers are the devices which are used to store and/or shift the bits of the input data word. Here the data bits can be made to enter (or exit) the register in serial/parallel mode in synchronization with the clock pulse. Moreover the data bits within the shift register can be made to change their position by moving towards right or left for each clock pulse.
Consider a 3-bit register formed by connecting three synchronous positive edge triggered D flip-flops as shown in Figure 1. Here it is seen that the CLR pins of all the flip-flops are tied-up together and are connected to the clear input. Further the output of FF1 (Q1) is connected as an input to flip-flop 2 (D2 of FF2) and the output of FF2, Q2 is connected as an input to flip-flop 3 (D3 of FF3). Moreover the data word which is to be stored is supplied to the register via the input pin of flip-flop 1 (D1 of FF1) while the data is collected from the output pin of third flip-flop (Q3 of FF3).

3 bit shift register circuit Generally the contents of every flip-flop (and hence the entire register) is made zero by driving their clear pins high before feeding the data. Next the first bit of the input word (B1 of Data in) is made to appear at D1.

This bit will be stored in FF1 and thereby appears at its output Q1 on the appearance of first leading edge of the clock. Further at the second clock tick, B1 is stored in FF2 and is obtained at Q2 while the data at Q1 will the second bit of the input word, B2. Similarly at the rising edge of the third clock pulse, the third bit of the input data word, B3 appears at Q1 while Q2 = B2 and Q2 = B1.
This is called right-shift data transmission as one can note the movement of data from left to right within the register. The operation of such a register is further emphasized by Figure 2 in terms of wave forms and by Table I which indicates the movement of data bits (green arrows), considering the data-in sequence as 100100. input output waveform for 4 bit buffer register right shift of data bits in the shift register In the type of shift register explained above it is seen that the data bit stored in the last flip-flop is lost as and when the new data bit is stored into the register. This can be avoided by back-connecting the output pin of FF3 to the D1 pin of FF1. This causes the output bit of the FF3 (Q3) to be stored into FF1 which results in the circulation of the data bits within the register. However even in this case the movement of data bits within the intermediate flip-flops remains the same.
Similar to the right-shift register, there are left-shift registers in which the data moves from right to left within the register. Further in some cases, the data loading and retrieval processes of the shift registers are controlled using additional circuitry. Never the less the basic functionality remains the same. Moreover one has to note that the mode of data movement explained remains the same irrespective of the size of the shift register.

Closely Related Articles Latches and Flip FlopsS R Flip Flop S R LatchActive Low S R Latch and Flip FlopGated S R Latches or Clocked S R Flip FlopsD Flip Flop or D LatchJ K Flip FlopMaster Slave Flip FlopRead Only Memory | ROMProgrammable Logic DevicesProgrammable Array LogicApplication of Flip FlopsShift RegistersBuffer Register and Controlled Buffer RegisterSerial In Serial Out (SISO) Shift RegisterSerial in Parallel Out (SIPO) Shift RegisterParallel in Serial Out (PISO) Shift RegisterParallel in Parallel Out (PIPO) Shift RegisterUniversal Shift RegistersBidirectional Shift RegisterDynamic Shift RegisterApplications of Shift RegistersUninterruptible Power Supply | UPSConversion of Flip FlopsJohnson CounterSequence GeneratorRing CounterMore Related Articles Digital ElectronicsBoolean Algebra Theorems and Laws of Boolean AlgebraDe Morgan Theorem and Demorgans LawsTruth Tables for Digital LogicBinary Arithmetic Binary AdditionBinary SubtractionSimplifying Boolean Expression using K MapBinary DivisionExcess 3 Code Addition and SubtractionK Map or Karnaugh MapSwitching Algebra or Boolean AlgebraBinary MultiplicationParallel SubtractorBinary Adder Half and Full AdderBinary SubstractorSeven Segment DisplayBinary to Gray Code Converter and Grey to Binary Code ConverterBinary to BCD Code ConverterAnalog to Digital ConverterDigital Encoder or Binary EncoderBinary DecoderBasic Digital CounterDigital ComparatorBCD to Seven Segment DecoderParallel AdderParallel Adder or SubtractorMultiplexerDemultiplexer555 Timer and 555 Timer WorkingLook Ahead Carry AdderOR Operation | Logical OR OperationAND Operation | Logical AND OperationLogical OR GateLogical AND GateNOT GateUniversal Gate | NAND and NOR Gate as Universal GateNAND GateDiode and Transistor NAND Gate or DTL NAND Gate and NAND Gate ICsX OR Gate and X NOR GateTransistor Transistor Logic or TTLNOR GateFan Out of Logic GatesINHIBIT GateNMOS Logic and PMOS LogicSchmitt GatesLogic Families Significance and Types of Logic FamiliesBinary Number System | Binary to Decimal and Decimal to Binary ConversionBinary to Decimal and Decimal to Binary ConversionBCD or Binary Coded Decimal | BCD Conversion Addition SubtractionBinary to Octal and Octal Binary ConversionOctal to Decimal and Decimal to Octal ConversionBinary to Hexadecimal and Hex Binary ConversionHexadecimal to Decimal and Decimal to Hexadecimal ConversionGray Code | Binary to Gray Code and that to Binary ConversionOctal Number SystemDigital Logic Gates2′s Complement1′s ComplementASCII CodeHamming Code2s Complement ArithmeticError Detection and Correction Codes9s complement and 10s complement | SubtractionSome Common Applications of Logic GatesKeyboard EncoderAlphanumeric codes | ASCII code | EBCDIC code | UNICODENew Articles Series and Parallel Inductors Electric PowerMeasurement of Losses in Shunt ReactorThree Phase Shunt ReactorMeasurement of Insulation ResistanceAmpere's Circuital Law
electrical engineering app