Table I shows the truth table for the decoder of Figure 1 which shows that when the enable is low, all the output lines are low, no matter what the input sequence be. This indicates the OFF state of the decoder which can also be considered to be its reset state. Thus one has to drive high on the enable pin to realize the functionality of the decoder. Table I shows that for the input sequence I2I1I0 = 000, the output pin O0 of the decoder is high while all other bits (O7 down to O1) remain low. Likewise, for the input sequence of 001, only O1 is high. Similar observation shows that only one output line is high for any given input bit pattern i.e. O2 is high for 010, O3 is high for 011, O4 is high for 100, O5 is high for 101, O6 is high for 110 and O7 is high for 111. Thus the Boolean equations for the outputs of the 3 to 8 decoder shown in Figure 1 are given by Equations (1) to (8) show that the decoder of Figure 1 can be designed using AND gate and NOT gate as shown by Figure 2. This is due to the fact that the output lines are nothing but the logical and of either input (blue lines) or its negation (red lines) with the enable signal (black line). The analogy presented here for 3 to 8 decoder holds good for any n to 2n decoder. However the output bit pattern need not be the same as the one explained. These kind of decoders are used in the applications such as data multiplexing, seven segment display and so on.