Serial in Serial Out (SISO) Shift RegisterPublished on 24/2/2012 & updated on Friday 18th of May 2018 at 11:58:20 AM
Initially all the flip-flops in the register are cleared by applying high on their clear pins. Next the input data word is fed serially to FF1. This causes the bit appearing at the D1 pin (B1) to be stored into FF1 as soon as the first leading edge of the clock appears. Further at the second clock tick, B1 gets stored into FF2 while a new bit enters into FF1 (B2).
This kind of shift in data bits continues for every rising edge of the clock pulse. This indicates that for every single clock pulse the data within the register moves towards right by a single bit. Thus the design shown in Figure 1 is regarded as a right-shift SISO shift register. Following the data transmission as explained, one can note that the first bit of an input word appears at the output of nth flip-flop for the nth clock tick. On applying further clock cycles, one gets the next successive bits of the input data word as the serial output (Table I). The waveforms pertaining to the same are shown by Figure 2.
Similar to the right-shift SISO shift-register shown, there can exist a left-shift SISO shift-register also (Figure 3). However the working principle remains the same except the fact that the data movement will be from right to left.
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