# Serial In Serial Out (SISO) Shift Register

**Serial In Serial Out (SISO) shift registers**are a kind of shift registers where both data loading as well as data retrieval to/from the shift register occurs in serial-mode. Figure 1 shows a n-bit synchronous

**SISO shift register**sensitive to positive edge of the clock pulse. Here the data word which is to be stored is fed bit-by-bit at the input of the first flip-flop. Further it is seen that the inputs of all other flip-flops (except the first flip-flop FF

_{1}) are driven by the outputs of the preceding ones say for example, the input of FF

_{2}is driven by the output of FF

_{1}. At last the data stored within the register is obtained at the output pin of the n

^{th}flip-flop in serial-fashion. Initially all the flip-flops in the register are cleared by applying high on their clear pins. Next the input data word is fed serially to FF

_{1}. This causes the bit appearing at the D

_{1}pin (B

_{1}) to be stored into FF

_{1}as soon as the first leading edge of the clock appears. Further at the second clock tick, B

_{1}gets stored into FF

_{2}while a new bit enters into FF

_{1}(B

_{2}).

This kind of shift in data bits continues for every rising edge of the clock pulse. This indicates that for every single clock pulse the data within the register moves towards right by a single bit. Thus the design shown in Figure 1 is regarded as a right-shift **SISO shift register**. Following the data transmission as explained, one can note that the first bit of an input word appears at the output of n^{th} flip-flop for the n^{th} clock tick. On applying further clock cycles, one gets the next successive bits of the input data word as the serial output (Table I). The waveforms pertaining to the same are shown by Figure 2.
Similar to the right-shift SISO shift-register shown, there can exist a left-shift SISO shift-register also (Figure 3). However the working principle remains the same except the fact that the data movement will be from right to left.

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