# Serial in Parallel Out (SIPO) Shift Register

**Serial In Parallel Out (SIPO) shift registers**, the data is stored into the register serially while it is retrieved from it in parallel-fashion. Figure 1 shows an n-bit synchronous

**SIPO shift register**sensitive to positive edge of the clock pulse. Here the data word which is to be stored (Data in) is fed serially at the input of the first flip-flop (D

_{1}of FF

_{1}). It is also seen that the inputs of all other flip-flops (except the first flip-flop FF

_{1}) are driven by the outputs of the preceding ones say for example, the input of FF

_{2}is driven by the output of FF

_{1}. In this kind of shift register, the data stored within the register is obtained as a parallel-output data word (Data out) at the individual output pins of the flip-flops (Q

_{1}to Q

_{n}). In general, the register contents are cleared by applying high on the clear pins of all the flip-flops at the initial stage. After this, the first bit, B

_{1}of the input data word is fed at the D

_{1}pin of FF

_{1}.

This bit (B_{1}) will enter into FF_{1}, get stored and thereby appears at its output Q_{1} on the appearance of first leading edge of the clock. Further at the second clock tick, the bit B_{1} right-shifts and gets stored into FF_{2} while appearing at its output pin Q_{2} while a new bit, B_{2} enters into FF_{1}. Similarly at each clock tick the data within the register moves towards right by a single bit while a new bit of the input word enters into the register. Meanwhile one can extract the bits stored within the register in parallel-fashion at the individual flip-flop outputs.
Analyzing on the same grounds, one can note that the n-bit input data word is obtained as an n-bit output data word from the shift register at the rising edge of the n^{th} clock pulse. This working of the shift-register can be summarized as in Table I and the corresponding wave forms are given by Figure 2.
In the right-shift SIPO shift-register, data bits shift from left to right for each clock tick. However if the data bits are made to shift from right to left in the same design, one gets a left-shift SIPO shift-register as shown by Figure 3. Nevertheless the basic working principle remains the same except the fact that now B_{n} down to B_{1} is stored in Q_{n} down to Q_{1} i.e. Q_{1} = B_{1}, Q_{2} = B_{2} … Q_{n} = B_{n} at the n^{th }clock tick.

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