n-channel JFET and p-channel JFET
Junction Field Effect Transistors (JFETs) are a type of FETs (high input impedance devices) which have three terminals namely, Source (S), Gate (G) and Drain (D). These devices are also called voltage controlled devices as the voltage applied at the gate terminal determines the amount of current flowing in-between the drain and the source terminals. FETs can either be composed of pn- or Schottky-junction due to which they are called pn JFETs or Metal Semiconductor FETs (MESFETs), respectively. Further, the pn JFETs can be classified into two types viz., (i) n-channel JFET and (ii) p-channel JFET, depending on whether the current flow is due to electrons or holes, respectively.
n-channel JFETThe schematic of an n-channel JFET along with its circuit symbol is shown in Figure 1. From the layered structure shown by Figure 1a, it is clear that the n-channel JFET has its major portion made of n-type semiconductor. The mutually-opposite two faces of this bulk material from the source and the drain terminals. Further, it is also seen that there are two relatively-small p-regions embedded into this substrate which are internally joined together to form the gate terminal. Thus, here, the source and the drain terminals are of n-type while the gate is of p-type. Due to this, two pn junctions will be formed within the device, whose analysis reveals the mode in which the JFET works. Further the circuit symbol shown by Figure 1b has an arrow pointing towards the device at its Gate terminal which indicates the direction in which the current would flow, provided the pn junction is forward biased.
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Working of n-channel JFETIn n-channel JFET, the majority charge carriers will be the electrons as the channel formed in-between the source and the drain is of n-type. Further, the working of these devices depends upon the voltages applied at its terminals (Figure 2).
Case I: Consider the case where no voltage is applied to the device i.e. VDS = 0 and VGS = 0. At this state, the device will be idle and no current flows through it i.e. IDS = 0. Case II: Now consider that the drain terminal of the device is connected to the positive terminal of the battery while its negative is connected to the source i.e. VDS = +ve. However let the gate terminal remain at unbiased state, which means VGS = 0. At this instant, the electrons within the n-substrate of the device start moving towards the drain being attracted by the positive force exerted by the battery. At the same time, the electron will also be repelled from the source as it is connected to the negative terminal of the voltage supply. This results in a net flow of current from drain to source (as per conventional direction) whose value is restricted only by the resistance offered to it by the channel. Further, it is seen that the increase in VDS increases the current flowing through the device at an initial state which can be termed to be JFET's Ohmic region. However, it is to be noted that the increase in VDS also causes an increase in the width of the depletion regions surrounding the pn junctions. This inturn causes the channel width to reduce, thereby increasing its resistance. This phenomenon continues till both of the depletion regions grow upto an extent wherein they almost seem to touch each other, a condition referred to as pinch-off. The corresponding value of VDS is referred to as pinch-off voltage, VP. Nevertheless, even in this case, a narrow channel with high current density exists within the device due to which IDS will get saturated to a level of IDSS as indicated in Figure 2. It is this behaviour of the JFET which causes it to behave as a constant current source. Case III: Next, for the set-up described in Case II, let us add the voltage source at the gate terminal such that the gate is negative w.r.t source i.e. VGS = -ve while VDS is +ve. In this case, the device behaves in a way very-similar to that in Case II, but for a lower value of VDS. This means that the pinch-off and the saturation occur quite earlier and are decided by the negative potential applied at the gate i.e. more negative the VGS, earlier the pinch-off due to which earlier will be the saturation, reducing IDSS (Figure 3). As the phenomenon continues, it is seen that a condition arises wherein the saturation level of the drain-to-source current I¬DS occurs right for a value of 0 mA. This means that there is no current flow through the device and essentially the device will turn OFF. The value of VDS for which this happens will be nothing but the negative pinch-off voltage i.e. VDS = -VP.
p-channel JFETThe p-channel JFET (Figure 4a) exhibits the mode of working which is similar to that of its counter-part, the n-channel JFET except a few differences. In the case of p-channel JFET, the major portion made of the device is made of p-type into which embedded are the two small n-type regions. Thus it has an n-type gate terminal and p-type source and drain, causing the channel to be of p-type where the holes will be the majority charge carriers. Next, the direction of the arrow in its circuit symbol is pointing outwards unlike in the case of n-channel JFETs (Figure 4b).
Working of p-channel JFETSimilar to the case of n-channel JFETs, the working of these devices also depends upon the voltages applied at its terminals (Figure 5). Case I: If VDS = 0 and VGS = 0, the device will be idle with no current i.e. IDS = 0. Case II: Now consider VDS to be –ve while VGS is 0. At this state, the current flows from the source to the drain (as per conventional direction) as the holes within the p-substrate move towards the drain while being repelled from the source. The value of this current is restricted only by the channel-resistance and is seen to increase with a decrease in VDS (Ohmic region). However once the pinch-off occurs (VDS = VP), the current IDS saturates at a particular level IDSS, during which the device acts like a constant current source (Figure 6). Case III: Next, let VGS = +ve while VDS is -ve. Here the effect exhibited is similar to that in Case II with the fact that the saturation occurs at a faster rate as the VGS becomes more and more positive. Similar to that seen in n-channel JFETs, even here the current ceases to flow as the value of VDS becomes equal to VP, turning the device into OFF state.
|Z||ZIA commented on 17/07/2018|
|M||MARTIN commented on 17/04/2018|
So the gate voltage is more positive than the source and the drain?