Master Slave Flip Flop

Master Slave flip flop are the cascaded combination of two flip-flops among which the first is designated as master flip-flop while the next is called slave flip-flop (Figure 1). Here the master flip-flop is triggered by the external clock pulse train while the slave is activated at its inversion i.e. if the master is positive edge-triggered, then the slave is negative-edge triggered and vice-versa. This means that the data enters into the flip-flop at leading/trailing edge of the clock pulse while it is obtained at the output pins during trailing/leading edge of the clock pulse. Hence a master-slave flip-flop completes its operation only after the appearance of one full clock pulse for which they are also known as pulse-triggered flip-flops. master slave flip flop The internal structure of a master-slave JK flip-flop interms of NAND gates and an inverter (to complement the clock signal) is shown in Figure 2. Here it is seen that the NAND gate 1 (N1) has three inputs viz., external clock pulse (Clock), input J and output Q̅; while the NAND gate 2 (N2) has external clock pulse (Clock), input K and output Q as its inputs.

Further the outputs of N1 and N2 gates are connected as the inputs for the criss-cross connected gates N3 and N4. These four gates together (N1, N2, N3 and N4) form the master-part of the flip-flop while a similar arrangement of the other four gates N5, N6, N7 and N8 form the slave-part of it. master slave flip flop From figure it is also evident that the slave is driven by the outputs of the master (M1 and M2), which is in accordance with its name master-slave flip-flop. Further the master is active during the positive edge of the clock due to which M1 and M2 change their states; depending on the values of J and K. However at this instant the outputs of the overall system (master-slave JK flip-flop) remains unchanged as the slave will be inactive due to positive-edge of the clock pulse. Similar to this, the slave decides on its outputs Q and Q̅ depending on its inputs M1 and M2, during the negative edge of the clock during which the master will be inactive.

The truth table corresponding to the working of the flip-flop shown in Figure 2 is given by Table I. Here it is seen that the outputs at the master-part of the flip-flop (data enclosed in red boxes) appear during the positive-edge of the clock (red arrow). However at this instant the slave-outputs remain latched or unchanged. The same data is transferred to the output pins of the master-slave flip-flop (data enclosed in blue boxes) by the slave during the negative edge of the clock pulse (blue arrow). The same principle is further emphasized in the timing diagram of master-slave flip-flop shown by Figure 3. Here the green arrows are used to indicate that the slave-output is nothing but the master-output delayed by half-a-clock cycle.
Moreover it is to be noted that the working of any other type of master-slave flip-flop is analogous to that of the master slave JK flip-flop explained here. truth table for master-slave jk flip flop master slave flip flop

Closely Related Articles Latches and Flip FlopsS R Flip Flop S R LatchActive Low S R Latch and Flip FlopGated S R Latches or Clocked S R Flip FlopsD Flip Flop or D LatchJ K Flip FlopRead Only Memory | ROMProgrammable Logic DevicesProgrammable Array LogicApplication of Flip FlopsShift RegistersBuffer Register and Controlled Buffer RegisterData Transfer in Shift RegistersSerial In Serial Out (SISO) Shift RegisterSerial in Parallel Out (SIPO) Shift RegisterParallel in Serial Out (PISO) Shift RegisterParallel in Parallel Out (PIPO) Shift RegisterUniversal Shift RegistersBidirectional Shift RegisterDynamic Shift RegisterApplications of Shift RegistersUninterruptible Power Supply | UPSConversion of Flip FlopsJohnson CounterSequence GeneratorRing CounterMore Related Articles Digital ElectronicsBoolean Algebra Theorems and Laws of Boolean AlgebraDe Morgan Theorem and Demorgans LawsTruth Tables for Digital LogicBinary Arithmetic Binary AdditionBinary SubtractionSimplifying Boolean Expression using K MapBinary DivisionExcess 3 Code Addition and SubtractionK Map or Karnaugh MapSwitching Algebra or Boolean AlgebraBinary MultiplicationParallel SubtractorBinary Adder Half and Full AdderBinary SubstractorSeven Segment DisplayBinary to Gray Code Converter and Grey to Binary Code ConverterBinary to BCD Code ConverterAnalog to Digital ConverterDigital Encoder or Binary EncoderBinary DecoderBasic Digital CounterDigital ComparatorBCD to Seven Segment DecoderParallel AdderParallel Adder or SubtractorMultiplexerDemultiplexer555 Timer and 555 Timer WorkingLook Ahead Carry AdderOR Operation | Logical OR OperationAND Operation | Logical AND OperationLogical OR GateLogical AND GateNOT GateUniversal Gate | NAND and NOR Gate as Universal GateNAND GateDiode and Transistor NAND Gate or DTL NAND Gate and NAND Gate ICsX OR Gate and X NOR GateTransistor Transistor Logic or TTLNOR GateFan Out of Logic GatesINHIBIT GateNMOS Logic and PMOS LogicSchmitt GatesLogic Families Significance and Types of Logic FamiliesBinary Number System | Binary to Decimal and Decimal to Binary ConversionBinary to Decimal and Decimal to Binary ConversionBCD or Binary Coded Decimal | BCD Conversion Addition SubtractionBinary to Octal and Octal Binary ConversionOctal to Decimal and Decimal to Octal ConversionBinary to Hexadecimal and Hex Binary ConversionHexadecimal to Decimal and Decimal to Hexadecimal ConversionGray Code | Binary to Gray Code and that to Binary ConversionOctal Number SystemDigital Logic Gates2′s Complement1′s ComplementASCII CodeHamming Code2s Complement ArithmeticError Detection and Correction Codes9s complement and 10s complement | SubtractionSome Common Applications of Logic GatesKeyboard EncoderAlphanumeric codes | ASCII code | EBCDIC code | UNICODENew Articles Series and Parallel Inductors Electric PowerMeasurement of Losses in Shunt ReactorThree Phase Shunt ReactorMeasurement of Insulation ResistanceAmpere's Circuital Law
electrical engineering app