Master Slave Flip FlopPublished on 24/2/2012 & updated on Thursday 17th of May 2018 at 04:12:35 PM
The internal structure of a master-slave JK flip-flop interms of NAND gates and an inverter (to complement the clock signal) is shown in Figure 2. Here it is seen that the NAND gate 1 (N1) has three inputs viz., external clock pulse (Clock), input J and output Q̅; while the NAND gate 2 (N2) has external clock pulse (Clock), input K and output Q as its inputs.
Further the outputs of N1 and N2 gates are connected as the inputs for the criss-cross connected gates N3 and N4. These four gates together (N1, N2, N3 and N4) form the master-part of the flip-flop while a similar arrangement of the other four gates N5, N6, N7 and N8 form the slave-part of it.
From figure it is also evident that the slave is driven by the outputs of the master (M1 and M2), which is in accordance with its name master-slave flip-flop. Further the master is active during the positive edge of the clock due to which M1 and M2 change their states; depending on the values of J and K. However at this instant the outputs of the overall system (master-slave JK flip-flop) remains unchanged as the slave will be inactive due to positive-edge of the clock pulse. Similar to this, the slave decides on its outputs Q and Q̅ depending on its inputs M1 and M2, during the negative edge of the clock during which the master will be inactive.
The truth table corresponding to the working of the flip-flop shown in Figure 2 is given by Table I. Here it is seen that the outputs at the master-part of the flip-flop (data enclosed in red boxes) appear during the positive-edge of the clock (red arrow). However at this instant the slave-outputs remain latched or unchanged. The same data is transferred to the output pins of the master-slave flip-flop (data enclosed in blue boxes) by the slave during the negative edge of the clock pulse (blue arrow). The same principle is further emphasized in the timing diagram of master-slave flip-flop shown by Figure 3. Here the green arrows are used to indicate that the slave-output is nothing but the master-output delayed by half-a-clock cycle. Moreover it is to be noted that the working of any other type of master-slave flip-flop is analogous to that of the master slave JK flip-flop explained here.
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