# Bidirectional Shift Register

**are the storage devices which are capable of shifting the data either right or left depending on the mode selected. Figure 1 shows an n-bit bidirectional shift register with serial data loading and retrieval capacity. Initially all the flip-flops in the register are reset by driving their clear pins high. Next R/LÌ… control line is made either low or high in order to opt for either left-shift or right-shift of the data bits, respectively. Now if R/L̅ = 1, then A**

*Bidirectional shift registers*_{1}gates of all the combinational circuits get activated while the A

_{2}gates will get disabled at the same time. Due to this, the outputs of each flip-flop appear at the inputs of the very-next flip-flop via OR gate output (except for the last flip-flop FFn).

For example, Q_{1} appears at D_{2} via the output of OR gate 1 (O_{1}), Q_{2} appears at D_{3} via the output of OR gate 2 (O_{2}), … and Q_{n-1} appears at D_{n} via the output of OR gate 1 (O_{n}) (red lines). At this instant if the positive edge of the clock pulse appears, then the outputs of the respective flip-flops reflect their inputs. Thus Q_{1} = D_{1}, Q_{2} = Q_{1},… and Q_{n} = Q_{n-1}. This is nothing but right-shift of the data by a single bit within the register. Following on the same grounds, one can note that for every rising edge of the clock, the data within the register shifts right by a single bit as long as R/L̅ remains high.

On the other hand, if R/L̅ goes low, then A_{2} gates of the combinational circuits get enabled while A_{1} gates get deactivated. This causes the outputs of each flip-flop to appear at the input pins of the very-previous flip-flop through their OR gate outputs (except the first flip-flop, FF_{1}). For example, Q_{n} appears at D_{n-1} through the output of OR gate n-1 (O_{n-1}), … Q_{3} appears at D_{2} via the output of OR gate 2 (O_{2}), and Q_{2} appears at D_{1} via the output of OR gate 1 (O_{1}). These input bits are latched onto their respective output pins as soon as the leading edge of the clock pulse appears and thus Q_{n-1} = Q_{n}, …Q_{2} = Q_{3} and Q_{1} = Q_{2} (green lines). This means that for every clock tick, the data within the register moves left by one bit, provided R/L̅ line is zero.

The working of such bidirectional register can be summarized as in Table I and can be further explained by the output wave forms shown by Figure 2.

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