MCQs on Microprocessor

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01․ Maximum number of I/O that can be addressed by the INTEL 8085 is
65536
285
512
256

I/O has 8 bit port address so maximum number of I/O that can be addressed by the INTEL 8085 is 28=256
02․ The microprocessor may be made to exit from HALT state by asserting
RESTART
any of the five interrupt lines
READY line
A or B or HOLD line

The microprocessor may be made to exit from HALT state by asserting RESTART or any of the five interrupt lines or HOLD line.
03․ In order to complement the lower nibble of accumulator one can use
ANI 0FH
XRI 0FH
ORI 0FH
CMA

By XRI operation the 8 bit data are exclusive ORed with the contents of the accumulator and results are placed in the accumulator.Let the content of accumulator is 0101 1010. Now EXORing it with 0FH = (0000 1111)2. We will get the answer 0101 0101 which will be stored in the accumulator. Hence we can see XRI 0FH instruction can be used to complement the content of lower nibble of accumulator.
04․ The 8085 microprocessor enters into bus idle machine cycle whenever
INTR interrupt is recognized
RST 7.5 is recognized
DAD RP instruction is executed
none of the above

When RST 7.5 is recognized the 8085 microprocessor enters into bus idle machine cycle.
05․ During OPCODE fetch the state of S0 and S1 is
00
01
10
11

S0 and S1 are status signal for different operation like HALT,WRITE,READ,and FETCH.During OPCODE fetch S0 = 1 and S1 = 1.
06․ After RESET 8255 will be in
mode 0; all ports are input
mode 0; all ports are output
mode 2
unchanged condition

In INTEL 8255, RESET is a active high signal which clears the control register and sets all the ports in the input mode or mode 0.
07․ The microprocessor issues ALE during first T-state of
fetch cycle only
memory READ cycle only
memory WRITE cycle only
every machine cycle

ALE is address latch enable signal.The microprocessor issues ALE or it goes high during first clock cycle of every machine cycle.
08․ The data lines of 8085 microprocessor are multiplexed with
higher order address lines
lower order address lines
status lines
none of the above

AD0 to AD7 can be used for both transmit data or address at different moments.Thus these bus operate in time sharing mode which is called multiplexing.The data lines of 8085 microprocessor are multiplexed with lower order address lines to increase the effective width of address bus.
09․ RST 3 instruction will cause the processor to branch to the location
0000H
0018H
0024H
0028H

For every vectored interrupt irrespective of software and hardware 8-bytes are allocated.Generally the allocated memory address will be 8*interrupt and its equivalent hexadecimal value. Example for RST 3 the memory address location would be 8*3=(24)10=(18)H.So the correct ans will be (0018)H.
10․ Which of the following instruction will never affect the zero flag?
DCR R
ORA R
DCX Rp
XRA R

By DCR B, the contents of the register is decreased by 1.The zero flag is affected but the carry flag is not affected. Due to ORA R the contents of the accumulator is ORed with the contents of register R.Zero and carry flag both are affected. Due to DCX Rp instruction register pair is decremented by1, no flags will be affected i.e. zero flag also will be unaffected. Due to XRA R the content of accumulator is Ex-ORed with register R, both zero and carry flag is affected.
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