# MCQs on Digital Electronics

##### Page 26 of 35. Go to page 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
01․ The most suitable gate for comparing two bits is
AND
OR
NAND
X-OR

One of the most commonly used application of X-OR gate is as a basic logic comparator which produces a logic ‘1’ output when its two inputs bits are not equal. Because of this, the X-OR gate has an inequality status being known as an odd function.

02․ Which of the following gates cannot be used as an inverter?
NAND
AND
NOR
X-NOR

NAND and NOR gares are universal gates. Therefore we can implement any gate by using either NAND or NOR gate. X-NOR gate will acts as an inverter when one of the inputs is low. Therefore, NAND, NOR and X-NOR gates can be used as inverter.

03․ A gate is enabled when its enable input is at logic 1. The gate is
OR
NAND
NOR
none of these

The output of AND gate is high when all inputs are high and output of AND gate is low when any one of the inputs is low. NAND gate output is low when all inputs are high and output of NAND gate is high only when at least one of input is low. Therefore, NAND gates and AND gates are enable when its enable input is logic ‘1’.

04․ A gate is enabled when its enable input is at logic 0. The gate is
NOR
AND
NAND
none of these

The output of OR gate is high when at least one input is high and output of OR gate is low when all inputs are low. NOR gate output is low when at least one input is high and output of NOR gate is high only when all the inputs are low. Therefore, NOR gates and OR gates are enable when its enable input is logic ‘0’.

05․ A gate is inhibited when its inhibit input is at logic 1. The gate is
AND
NAND
OR
none of these

The output of OR gate is high when at least one input is high and output of OR gate is low when all inputs are low. NOR gate output is low when at least one input is high and output of NOR gate is high only when all the inputs are low. Therefore, NOR gates and OR gates are disable when its disable input is logic ‘1’.

06․ A gate is disabled when its disable input is at logic 0. The gate is
AND
NOR
OR
none of these

The output of AND gate is high when all inputs are high and output of AND gate is low when any one of the inputs is low. NAND gate output is low when all inputs are high and output of NAND gate is high only when at least one of input is low. Therefore, NAND gates and AND gates are disable when its disable input is logic ‘0’.

07․ The output of a logic gate is 1 when all its inputs are at logic 1. The gate is either
a NAND or a NOR
an AND or an OR
an OR or an X-OR
an AND or a NOR

The output of AND gate is high when all inputs are high and the output of OR gate is high when at least one input is high. Therefore, the output of a logic gate is 1 when all its inputs are at logic 1, the gate is either an AND or an OR.

08․ The output of a logic gate is 1 when all its inputs are at logic 0. The gate is either
a NAND or a NOR
an AND or an X-NOR
an OR or a NAND
an X-OR or an X-NOR

The output of NAND gate is high only when at least one of input is low and the output of NOR gate is high only when all the inputs are low. Therefore, the output of a logic gate is 1 when all its inputs are at logic 0, the gate is a NAND or a NOR.

09․ The output of a logic gate is 1 when all its inputs are at logic 1. The gate is either
an OR or an X-OR
a NAND or an X-NOR
an AND or a NAND
an OR or an X-NOR

The output of OR gate is high when at least one input is high and the output of X-NOR gate is high only when the all inputs are logic ‘0’ or logic’1’.

10․ The output of a logic gate is 1 when all its inputs are at logic 0. The gate is either
a NOR or an X-NOR
a NAND or an X-OR
an OR or an X-NOR
an AND or an X-OR

The output of NOR gate is high only when all the inputs are low and the output of X-NOR gate is high only when the all inputs are logic ‘0’ or logic’1’.

<<<2425262728>>>