MCQs on Digital Electronics

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01․ The code used for labeling the cells of a K-map is
8-4-2-1 binary
hexadecimal
gray
octal

The sequence used in k map is not in binary sequence which would be 00, 01, 10, 11. It is 00, 01, 11 10, which is Gray code sequence. Gray code sequence only changes one binary bit as we go from one number to the next in the sequence, unlike binary. That means that adjacent cells will only vary by one bit, or Boolean variable. This is what we need to organize the outputs of a logic function so that we may view commonality. Moreover, the column and row headings must be in Gray code order, or the map will not work as a Karnaugh map.
02․ The number of cells in a 6 variable K-map is
6
12
36
64

K-maps are ways of minimizing the Boolean functions using diagrams which are made up of squares. By minimization we imply a function with minimum number of terms and each term with lowest number of literals. Anytime you have n variables, you will have 2n cells possible combinations, and 2n cells places in a truth table or Karnaugh Map. Therefore, number of cells = 26 = 64
03․ The Quine– McClusky method of minimization of a logic expression is a (i) graphical method (ii) algebraic method (iii) tabular method (iv) a computer-oriented algorithm The correct answers are
(iii) and (iv)
(ii) and (iv)
(i) and (iii)
(i) and (ii)

The Quine–McCluskey algorithm (or the method of prime implicants) is a method used for minimization of boolean functions. It is functionally identical to Karnaugh mapping, but the tabular form makes it more efficient for use in computer algorithms, and it also gives a deterministic way to check that the minimal form of a Boolean function has been reached. It is sometimes referred to as the tabulation method.
04․ In simplification of a Boolean function of n variables, a group of 2m adjacent 1s leads to a term with
m – 1 literals less than the total number of variables
m + 1 literals less than the total number of variables
n + m literals
n – m literals

K- map is a graphical representation and can be used to minimize the logical expression with 'o', '1' and don't care. In k- map, group of 8 cells is called as octet, it will eliminates 3 variables in given expression. (23 = 8) Similarly, a group of 2m cells will eliminate 'm' variables. Therefore, final expression will contain 'n-m' literals.
05․ A 16-square eliminates
2 variables
3 variables
4 variables
8 variables

In k- map, group of 8 cells is called as octet, it will eliminates 3 variables in given expression. (23 = 8) Similarly, a group of 2m cells will eliminate 'm' variables. Therefore, for given problem 4 variables will be eliminated.
06․ In K-map simplification, a group of four adjacent 1s leads to a term with
one literal less than the total number of variables
two literals less than the total number of variables
three literals less than the total number of variables
four literals less than the total number of variables

K- map is a graphical representation and can be used to minimize the logical expression with 'o', '1' and don't care. In k- map, group of 8 cells is called as octet, it will eliminates 3 variables in given expression. (23 = 8) A group of 4 cells is called as quad, it will eliminates 2 variables. Similarly, a group of 2m cells will eliminate 'm' variables. Therefore, final expression will contain 'n-m' literals.
07․ Minimization of logical expressions while designing digital systems helps in reducing
cost
space requirements
power requirements
all of the above.

The problem with having a complicated circuit (i.e. one with many elements, such as logical gates) is that each element takes more physical space in its implementation and cost is also more. Circuit minimization may be one form of logic optimization used to reduce the area of complex logic in integrated circuits as well as space and power requirements.
08․ The NAND-NAND realization is equivalent to
AND-NOT realization
AND-OR realization
OR-AND realization
NOT-OR realization

The NAND-NAND realization is equivalent to AND-OR realization. Bubbled inputs of OR gate will results a NAND gate and compliment of AND gate is a NAND gate. Therefore, NAND-NAND realization is equivalent to AND-OR realization.
09․ The NOR-NOR realization is equivalent to
AND-OR realization
NOT-AND realization
OR-NOT realization
OR-AND realization

The NOR-NOR realization is equivalent to OR-AND realization. Bubbled inputs of AND gate will results a NOR gate and compliment of OR gate is a NOR gate. Therefore, NOR-NOR realization is equivalent to OR-AND realization.
10․ AND-OR realization of a combinational circuit is equivalent to
NAND-NOR realization
NAND-NAND realization
NOR-NOR realization
NOR-NAND realization

The NAND-NAND realization is equivalent to AND-OR realization. Bubbled inputs of OR gate will results a NAND gate and compliment of AND gate is a NAND gate. Therefore, NAND-NAND realization is equivalent to AND-OR realization and vice versa.
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