# MCQs on Digital Electronics

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01․ How many flip flops are required to build a binary counter circuit to count from 0 to 1023?
6.
10.
24.
12.

Total count = 1024, 2N = 1024 or, 2N = 210 or, N = 10 (no. of flip flops).

02․ In flip flop clock is present but in latch clock is
present always.
absent always.
may be present/absent.
none.

Synchronous circuits change their states only when clock pulses are present.The latch with additional control input ( clock, enable input) is called flip flop.

03․ Counter is a
combinational circuit.
sequential circuit.
both.
none.

A counter is a sequential circuit that keeps a record of the clock pulses sent through it. Like a register, a counter also consists of a group of flip-flops. However, a counter has a characteristics internal sequence of states through which it passes when a series of clock pulses are fed to it. Counters are divided into categories : ripple ( or asynchronous ) counters and synchronous counters.

04․ The 2s complement of 17 is
101111.
110001.
101110.
111110.

17 = 010001, 1s complement = 101110, 2s complement = 101111.

05․ 1Ã¢â‚¬â„¢s complement of 17 is
01110.
10001.
10111.
11100.

17 = 10001, 1s complement of 17 = 01110. For 1s complement 0 is written as 1 and 1 is written as 0.

06․ A 10 bit A/D conveter is used to digitize an analog signal in the 0 to 6 volt. The maximum peak to ripple voltage that can be allowed in the D.C. supply voltage is
6 mV.
5 mV.
5.85 mV.
10 mV.

Smallest incremental change = 1 / 210 = 1 / 1024. So for 6 Volt incremental change = 6 / 1024 = 5.85 mV.

07․ If a counter having 10 flip flops is initially at 0, What count will if hold after 2060 pulses?
000 000 1000.
000 000 1110.
000 001 1100.
000 000 1100.

In complete one cycle 1024 pulses 2060 / 1024 =2048 / 2 cycles, Balance = 2060 - 2040 = 12 pulses. Binary no. of 12 is = 000 000 1100

08․ A switch-tail ring counter is made by using a single D-FF, the following circuit is
T FF.
D FF.
S-R FF.
J-K FF.

In a switch tail ring counter, using D FF, the complementary of output ( Q ) is connected to D input for a single D-FF it becomes a T FF.

09․ The fast logic family is
ECL.
DRL.
TRL.
TTL.

ECL ( Emitter coupled logic) is the fast logic family. Because the switching transistors do not go into saturation in either the on / off state. ECL is sensitive to a threshold level only.

10․ The set of which logic gates is designated as universal gate?
NOT, OR , AND.
XNOR, NOR, NAND.
NOR , NAND.
XNOR, NOR, NAND.

They are called universal gates because we can be constructed the other gates by using any one of those two gates.

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