MCQs on Digital Electronics

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01․ Which of the following memories uses one transistor and one capacitor as basic memory unit
SRAM
DRAM
Both SRAM and DRAM
None

Static RAM ( Random Access Memory ) is constructed by using two or more BJT or MOSFET, one for each stored bit. But in DRAM ( Dynamic Random Access Memory ) uses one MOSFET and one capacitor for storing one bit. Here transistor works as a switch and the capacitor stored binary information as electric charges.
02․ Which number system has a base of 16
Decimal
Octal
Hexadecimal
None

Decimal base = 10, Octal base = 8. Hexadecimal base = 16 ( 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F ). Where A = 10, B = 11, C = 12, D = 13, E = 14, F = 15. It is always represented by 4 bits in binary number system by 8421 code.
03․ A latch is ________ sensitive
both level and edge
edge
level
None

A latch works on level of a clock, means when the clock is high, all the effects of input will appear on output otherwise not. A flip-flop works on a clock edge either positive or negative, means when the clock edge come, the effect of inputs will appear on output otherwise not.
04․ How many entries will be in the truth table of a 3 input NAND gate ?
3
6
8
9

Y = 2n Y is number of Entries in the truth table, while n is the number of inputs.
05․ How many bits are required to store one BCD digit ?
1
2
3
4

BCD (Binary coded Decimal) Number is from 0 to 9, which requires four bits to store. As the maximum number of the system (15) can best represented by 4 bits. It is also called as 8421 code to represent maximum number 15.
06․ In binary number system the first digit (bit) from right to left is called as
LSB, Least Significant Bit
MSB, Most Significant Bit
First Bit
Last Bit

Starting from Left to Right, the first bit is called as MSB (Most Significant Bit). It also represents the signed or unsigned bit.
07․ In an SR latch built from NOR gates, which condition is not allowed
S=0, R=0
S=0, R=1
S=1, R=0
S=1, R=1

At S=0, R=0, Output of the latch becomes Q=0, B_bar=0, which is an unwanted state. also known as indeterminate state.
08․ A D-flip-flop is said to be transparent when
the output is LOW
the output is HIGH
the output follows clock
the output follow input

When the clock is enabled (en=1) for a D-flip-flop, the input is appeared at the output. So the flip-flop is said to be transparent.
09․ Which of these sets of logic gates are designated as universal gates?
NOR, NAND.
XOR, NOR, NAND.
OR, NOT, AND.
NOR, NAND, XNOR.

NAND or NOR gate can design all other logic gates. So, they are designated as universal gates.
10․ Which one of the following is not a vectored interrupt?
TRAP.
RST 7.5.
RST 6.5.
INTR.

In 8085 microprocessor TRAP, RST 7.5, RST 6.5, RST 5.5 are vectored interrupt. But RST 3 and INTR is a non vectored interrupt.
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